1. Field of the Invention
The present invention relates in general to non-volatile digital memories and, more particularly, to an improved cell structure for a programmable non-volatile memory (such as conventional EEPROM or Flash EEPROM) that can store up to eight-bits of information and a method for fabricating same.
2. Background Art
Non-volatile memory devices, such as EPROM, EEPROM, and flash EPROM devices, generally include a matrix of transistors which act as memory cells for storing a single-bit of information. Each transistor in this matrix has source and drain regions formed on a n- or p-type semiconductor substrate, a thin tunnel dielectric layer formed on the surface of the semiconductor substrate positioned at least between the source and drain regions, a floating gate (formed of polysilicon) positioned on the insulating layer for holding a charge, a control gate and an interpoly dielectric positioned between the floating gate and control gate.
Traditionally, the interpoly dielectric had consisted of a single layer of silicon dioxide (SiO2). However, more recently oxide/nitride/oxide composites (sometimes referred to as an ONO structure) have been used in place of the silicon dioxide because they exhibit decreased charge leakage over the single oxide layer (see Chang et al. U.S. Pat. No. 5,619,052).
U.S. Pat. No. 5,768,192 to Elian discloses that ONO structures (as well as other charge trapping dielectrics) have been used as both insulator and floating gate. Eitan teaches that by programming and reading this transistor device in opposite directions (i.e., reversing xe2x80x9csourcexe2x80x9d and xe2x80x9cdrainxe2x80x9d) shorter programming times still result in a high increase in exhibited threshold voltage. Eitan suggests that this result is useful in reducing programming time while still preventing xe2x80x9cpunch throughxe2x80x9d (i.e. condition where the lateral electric field is strong enough to draw electrons through to the drain, regardless of the applied threshold level).
The semiconductor memory industry has been researching various techniques and approaches to lower the bit cost of non-volatile memory. Two of the more important approaches are dimensional shrinking and multilevel storage. Multilevel storage (often referred to as multilevel cells) means that a single cell can represent more than one bit of data. In conventional memory cell design, only one bit has been represented by two different voltage levels, such as 0V and 5V (in association with some voltage margin), which represent 0 or 1. In multilevel storage more voltage ranges/current ranges are necessary to encode the multiple bits of data. The multiple ranges lead to reduced margins between ranges and require advanced design techniques. As a result, multilevel storage cells are difficult to design and manufacture. Some exhibit poor reliability. Some have slower read times than convention single-bit cells.
Accordingly, it is an object of the present invention to produce a non-volatile memory structure that achieves cost-savings by providing a structure capable of storing up to eight bits of data, thus significantly increasing the storage size of the non-volatile memory. It is an associated object of the present invention for this cell structure to operate without the use of reduced margins or advanced design techniques.
These and other objects will be apparent to those of ordinary skill in the art having the present drawings, specification and claims before them.
The present invention discloses a single cell non-volatile semiconductor memory device for storing up to eight-bits of information. The device has a semiconductor substrate of one conductivity type, a central bottom diffusion region on top of a portion of the semiconductor substrate, a second semiconductor layer on top of the bottom diffusion region, and left and right diffusion regions formed in the second semiconductor layer apart from the central bottom diffusion region thus forming a first vertical channel between the right and central bottom diffusion regions. The device further includes a trapping dielectric layer formed over exposed portions of the semiconductor substrate, left, central and right bottom diffusion regions and second semiconductor layer and a wordline formed over the trapping dielectric layer.
The foregoing structure can be fabricated by: (1) forming a semiconductor substrate of one conductivity type; (2) implanting ions in the semiconductor substrate a layer of conductivity type opposite to the conductivity type of the semiconductor substrate to form a bottom diffusion region; (3) growing a second semiconductor layer on at least a portion of said bottom diffusion region; (4) implanting ions in the second semiconductor layer to form in the second semiconductor layers, right and left diffusion regions of the same conductivity type; (5) trenching the resulting semiconductor wafer to form one or more free-standing cells on the semiconductor substrate; (6) depositing a trapping dielectric structure on the exposed faces of the free-standing cells and semiconductor substrate; and (7) depositing a polysilicon control gate on top of the trapping dielectric structure.